//Copyright (C)2014-2024 GOWIN Semiconductor Corporation.
//All rights reserved.
//File Title: Timing Constraints file
//Tool Version: V1.9.9 (64-bit) 
//Created Time: 2024-06-02 13:06:26
create_clock -name xtal_clk_in -period 20 -waveform {0 10} [get_ports {xtal_clk_in}]
create_generated_clock -name sys_clk -source [get_ports {xtal_clk_in}] -master_clock xtal_clk_in -divide_by 500 [get_pins {xtal_clk_div/g_even_div.clk_div_inst/clk_div_s1/Q}]
